1. Field of the Invention
The invention relates generally to digital CMOS (Complimentary Metal Oxide Semiconductor) circuits and more particularly to digital circuit design techniques in semiconductor devices which reduce output ringing in very fast CMOS output configurations.
2. Description of the Prior Art
The need for increasing levels of throughput and the resulting improved performance in today's CMOS systems requires high speed and high dynamic drive current that interface chips to circuit boards or backplanes. The high speed and high current drive levels can be easily achieved by modern submicron CMOS processing, but there are a few undesirable side effects.
Higher rates of change (di/dt) in all switching transistors result from the much faster slewing of the internal nodes in current technology devices. Output devices are designed to handle high levels of output current and the consequential di/dt can be exceedingly high. Some devices that have many of their outputs switching simultaneously can experience di/dt levels of 500 milliamps per nanosecond in their common ground or Vcc leads. A certain amount of inductance in these leads is unavoidable and significant voltages can be developed across relatively small inductive reactances when di/dt levels are high. The "lead" inductance often referred to in this connection usually includes the combination of bonding wire and package pin inductances.
FIG. 1 shows a prior art CMOS output driver arrangement and shows the package lead inductances as L.sub.1 -L.sub.3 and an external load capacitance C.sub.L that is fifty picofarads. Transistors N.sub.1 (NMOS) and P.sub.1 (PMOS) are designed to be large enough to source or sink about 100 mA. The typical high-speed CMOS chip has many such drivers that all share the same on-chip power and ground rails. A particular area of concern is the case where most of the outputs switch from logic HIGH to LOW by turning on transistors N.sub.1. This will generate a voltage fluctuation of the on-chip ground compared to the system ground. This condition is commonly known as "ground bounce." Too severe a ground bounce will cause false level transitions in both the driving and driven devices. Less severe ground bounce will decrease noise immunity, because positive ground bounce robs from Voltage Input High (V.sub.ih) margins and negative ground bounce cuts into Voltage Input Low (V.sub.IL) margins. Ground bounce effects are sensitive to process, temperature, and operating voltage variations. "Fast" processes, low temperatures, and high operating voltages can each increase ground bounce effects. Device speed, a dominant parameter, is the worst at the opposite extremes: slow processes, high temperatures, and low operating voltages. Testing for speed receives so much attention at its worst case extremes, that the worst case extremes for ground bounce are often ignored.
In FIG. 2, the positive half cycle ground bounce that peaks at "A" primarily results from the rate of change of current (di/dt) of one buffer times the ground lead inductance L.sub.1 times the number of buffers simultaneously switching their respective N.sub.1 devices to ON. The di/dt rate is determined by the rate at which the gate voltage (V.sub.g) to source voltage (V.sub.s) of N.sub.1 changes (dV.sub.gs /dt). During the first part of the output fall time, the ground voltage rises while the output voltage (V.sub.o) falls. This forces N.sub.1 into its linear region of operation. Transistor N.sub.1 then is the equivalent of a resistor having a resistance R.sub.on, and that can be as high as a few tens of ohms for a high-speed buffer. For the remainder of the output voltage excursion, the equivalent circuit of the output can be treated as if it were a resonant L-C-R circuit consisting of the ground and output lead inductance (L.sub.1 and L.sub.3), the load capacitance C.sub.L, and the total loop resistance which includes R.sub.on. The resonant frequency is determined by the net values of inductance and capacitance, while the damping is determined by the inductance and the total resistance of the loop. If L.sub.1 is large enough and R.sub.on is small enough, the ground bounce will oscillate through several Cycles, as shown in FIG. 2. False triggering can be caused if point "C" exceeds a logic HIGH. The whole of a device's noise margin can also be exceeded if the peak at point "A" (in a device having quiescent output at a logic LOW) rises higher than the input threshold of a circuit driven by the quiet output.
The prior art has attempted to correct ground bounce. Different approaches have been tried, but practically all have achieved less than a complete solution. The most common work-around solution has been to slow down the positive going rate-of-change of Vgs by inserting an appropriate delay network between Vg and the gate of N.sub.1. If N.sub.1 has a slow enough positive rise, then the amplitudes of points "A", "B", and "C" in FIG. 2 will be reduced. However, in order to have a significant ground bounce reduction, a buffer driving a fifty picofarad load might have to slow its HIGH to LOW transition from one and a half nanoseconds to six nanoseconds. The exact amount of slowdown required depends on the package pin inductances and the number of outputs that might be simultaneously switching. A delay that is enough for the case when all outputs are switching will be excessive for cases when fewer than that number are switching. With some devices now having as many as 32 outputs, the ground bounce solutions chosen can have a major influence in a device's high speed performance.
Another common technique employed to control ground bounce involves distributing the current running through pull-down devices. Multiple pulldown devices each handle a reduced portion of the whole current and are successively turned on via a delay chain. Consider the prior art found in U.S. Pat. No. 4,785,201 by Martinez. The circuit of Martinez uses a P-type Metal Oxide Semiconductor (PMOS) pull-up transistor and a N-type Metal Oxide Semiconductor (NMOS) pull-down transistor as a pair of strong driving elements. (The parasitic, but "unavoidable series inductance to system ground" is shown as a discrete inductor, and a matching inductor to V.sub.cc.) A PMOS pull-up transistor and a NMOS pull-down transistor form a pair of weak driving elements. The weaker pair are designed to turn on prior to the stronger pair via delays introduced by a pair of inverter transistors. The main idea is that the large current spike created when a large lumped device is turned on will be decreased in intensity if a previously activated weaker device dissipates some of the initial discharge energy. The gain of the stronger devices can be slightly lower than would otherwise be required. The U.S. Pat. No. of Bolar et al., 4,638,187, avoids using a PMOS pull-down as a weaker device, and instead uses another NMOS pulldown transistor. This weaker pull-down transistor has a smaller gain than the main NMOS pull-down. The delay is introduced by an R-C network that includes a resistor (and stray capacitance), instead of an inverter chain. U.S. Pat. No. 4,777,389, by Wu et al., discloses a circuit that essentially uses the same current distribution as above, but uses a different method of achieving the delay for the second, stronger pull-down transistor. The delay in turning on the second, stronger pull-down transistor results from a closed loop control that waits for the high to low transition of the output to reach a certain level before a pull-down transistor is activated. This assures an adequate time spacing between the two current spikes. None of the prior art above directly monitor or control the particular electrical parameter that results in ground bounce, namely, the time rate of change of the pull-down current (di/dt). The sensitivities to process, temperature, and operating voltage also go largely neglected. The U.S. Pat. No. 4,622,482, of Ganger, directs itself to limiting the output voltage slew rate in telecommunications applications. A pair of fixed capacitors, and a pair of constant current sources, are each used to perform slew rate limiting and to insure linearity. Several undesirable consequences result from the implementation. Biasing circuits are required to provide N-bias and P-bias potentials, thereby requiring an accurate source externally and therefore extra I/O pins. Alternatively, internally generated biases would necessitate generators with large static DC currents to sustain a reasonable noise rejection ratio. A complementary pair of push-pull transistors and are never mutually exclusive because their gates are not pulled completely up to Vdd or down to Vss when intended to be off. This results in large leakage currents that are usually unacceptable in digital circuits. And since the push-pull transistors are never quite off, parasitic capacitive coupling in their gates to Vdd and Vss will cause the push-pull transistors to amplify any high-frequency noise on the Vdd and Vss supply rails. Slew-rate control is confined only to the saturation region of the output transistors when static biasing is used. Since the value of capacitors do not change to accommodate the push-pull transistors transition from their saturation region to their linear region, the linearity control fails at this stage and throughout the linear region of operation. The capacitive coupling provided by capacitors will couple any output transition back to the gate of the supposedly off transistor to cause it to turn on. While the resulting current contention has the effect of further limiting the voltage slew rate of the output, it inadvertently dumps even more transient and DC current to Vss, which actually increases ground bounce in digital circuits.
Lien, et al., in U.S. Pat. No. 4,933,574, disclose a BiCMOS output driver that is intended to maximize switching speed and to minimize ground bounce. A bipolar transistor in the output is not permitted to go into saturation. A pair of transistors, connected in an inverter configuration, develop a signal that indicates when the bipolar transistor pulls-down the output below a predetermined point. Three gate delay times after the output falls below a second predetermined level, a second transistor in parallel with the bipolar transistor is switched.
The prior art has more-or-less been directed at controlling ground bounce for channels that are actively switching their outputs from high to low. The popular technique, described above, is to use two output pull-down transistors to ease up on the rate of output slew from high to low. What is needed is a solution that addresses the problem of quiescent channels that are already low and become unsettled by local ground bounce induced by a neighboring output channel. The present invention provides such a solution. Two output pull-down transistors in parallel decouple the quiescent, low channel from a local ground by turning-off the output transistor with the lower R.sub.on resistance, during positive swings of the local ground caused by ground bounce.